This invention relates to a semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor and a manufacturing method of the same.
There has been known a semiconductor integrated circuit device comprising an MOS (metal oxide semiconductor) or field effect transistor and a bipolar transistor. An MOS transistor operates at a high speed. A bipolar transistor has a high cut-off frequency and consumes less power. For forming a bipolar transistor, there has been generally prepared a two-layered silicon wafer comprising a semiconductor substrate of a conductivity type and an epitaxial semiconductor layer formed thereon of an opposite conductivity type, or a two-layered silicon wafer further comprising an embedded layer which is formed between the substrate and epitaxial layer and which has the same as that of the epitaxial layer as well as a high impurity concentration. For forming complementary MOS transistors, a single-layer silicon wafer has been prepared. When an N conductivity type single-layer silicon wafer having the impurity concentration of 1.times.10.sup.15 cm.sup.-3, for example, is prepared for forming complementary MOS transistors, a P well region whose surface impurity concentration is 1.times.10.sup.16 cm.sup.-3, for example, is formed in the silicon wafer. An N channel MOS transistor is formed in the P well region. A P channel MOS transistor is formed in the substrate.
On forming a bipolar transistor, the highest temperature possible is applied to the wafer at the heating step in which an impurity is diffused into the wafer to form an isolation region for electrically isolating the respective semiconductor circuit devices from each other. A high temperature of 1200.degree. C. is applied to the wafer for one or for one and one-half time period to form an isolation region of the thickness of 5 .mu.m. In this case, the surface resistance of the isolation region is about 5 to 50 .OMEGA./.quadrature.. In forming an MOS transistor, the highest temperature possible is applied to the wafer at the heating step in which a well region is formed. A temperature of 1190.degree. C. is applied to the wafer for 12 hours to form a well region of a thickness of 5 to 6 .mu.m.
The highest temperature applying step is commonly applied in order to form bipolar and MOS transistors so that the time for manufacturing the device is shortened. In this case, there is prepared a semiconductor wafer comprising a P substrate 11, an N.sup.+ embedded region 12 of a high impurity concentration formed on a P substrate 11 by an impurity diffusion process, and an N epitaxial layer 13 formed on the whole substrate surface (FIG. 1). Isolation P regions 14 for electrically isolating the respective integrated circuit device and P well regions 15 are first formed in the epitaxial layer 13. The heating step for the P well region 15 is set longer than that for the isolation regions 14. Therefore, only P well region 15 is first thermally heated for a predetermined period of time. Thereafter, the P well regions 15 and isolation regions 14 are commonly thermally heated. For example, a thermal oxidation film of about 1000 .ANG. is formed on the wafer. Then a boron ion with a low dose amount of about 10.sup.12 cm.sup.-2 is implanted into the P well region 15. Thereafter, the wafer is subjected to a heating process to diffuse the implanted ion in the P well 15. Next, a boron ion with a dose amount of about 10.sup.13 to 10.sup.14 cm.sup.-2 is implanted into the isolation regions 14 and then the P well 15 and the isolation region 14 are concurrently subjected to a heating process for impurity diffusion. The temperature at the concurrent heating step is about 1190.degree. C. Thus, regions where MOS transistor and bipolar transistors will be formed are formed in the wafer.
Bipolar transistors and CMOS transistors are then formed. Specifically, gate oxidation films 16.sub.1, 16.sub.2 of a P channel MOS transistor and an N channel MOS transistor are first formed, and then gate electrodes 17.sub.1, 17.sub.2 of polysilicon are formed on the film 16.sub.1, 16.sub.2, respectively. Next, a P type impurity is diffused into the wafer to form the source and drain regions 18 and 18' of the P channel MOS transistor Tr1, and to form the base regions 19 of the bipolar transistor Tr3. An N type of impurity is thereafter diffused into the wafer to form the source and drain regions 20 and 20' of the N channel MOS transistor Tr2, and to form the emitter and collector regions 21, 22 of the bipolar transistor Tr3.
However, with the conventional manufacturing method, in the heating step for impurity diffusion in the P well 15 and in the isolation regions 14, the impurity in the embedded layers 12 is largely diffused into the N epitaxial layer 13. It is difficult to keep the impurity concentration of that region of the epitaxial layer 13 which is on the embedded regions 12 in the drawings homogeneous. However, it is required that the bipolar transistor have an impurity concentration in the epitaxial layer 13 that is homogeneous. The reason for this is that the static characteristic and withstand voltage of the bipolar transistor are directly affected by the impurity concentration. Also, the threshold voltage of the MOS transistor varies when the impurity concentration is not homogeneous. With the conventional manufacturing method, the base and emitter regions of the bipolar transistor, and the source and drain regions of the MOS transistor are formed with the same or common steps. However, with this technique, it is difficult to provide satisfactory characteristics to both MOS and bipolar transistors.
In the conventional circuit device as shown in FIG. 1, an N.sup.+ impurity diffused region of a high impurity concentration and of a small thickness is generally formed in the collector region of bipolar transistor when it is required to reduce the collector resistance of the bipolar transistor and also to reduce the ON resistance. However, this complicates the manufacturing process of the device.